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DM9602 Dual Retriggerable, Resettable One Shots
August 1986 Revised February 2000
DM9602 Dual Retriggerable, Resettable One Shots
General Description
These dual resettable, retriggerable one shots have two inputs per function; one which is active HIGH, and one which is active LOW. This allows the designer to employ either leading-edge or trailing-edge triggering, which is independent of input transition times. When input conditions for triggering are met, a new cycle starts and the external capacitor is allowed to rapidly discharge and then charge again. The retriggerable feature permits output pulse widths to be extended. In fact a continuous true output can be maintained by having an input cycle time which is shorter than the output cycle time. The output pulse may then be terminated at any time by applying a LOW logic level to the RESET pin. Retriggering may be inhibited by either connecting the Q output to an active HIGH input, or the Q output to an active LOW input.
Features
s 70 ns to output width range s Resettable and retriggerable--0% to 100% duty cycle s TTL input gating--leading or trailing edge triggering s Complementary TTL outputs s Optional retrigger lock-out capability s Pulse width compensated for VCC and temperature variations
Ordering Code:
Order Number DM9602N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Logic Diagrams
Function Table
Pin Numbers A HL H X
H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care
B L LH X
CLR H H L
Operation Trigger Trigger Reset
(c) 2000 Fairchild Semiconductor Corporation
DS006611
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DM9602
Operating Rules
1. An external resistor (RX) and external capacitor (CX) are required as shown in the Logic Diagram. 2. The value of CX may vary from 0 to any necessary value available. If, however, the capacitor has leakages approaching 3.0 A or if stray capacitance from either terminal to ground is more than 50 pF, the timing equations may not represent the pulse width obtained. 3. The output pulse with (t) is defined as follows: 6. Under any operating condition, CX and RX (min) must be kept as close to the circuit as possible to minimize stray capacitance and reduce noise pickup. 7. Input Trigger Pulse Rules (See Triggering Truth Table)
This configuration is not recommended with retriggerable operation.
5. To obtain variable pulse width by remote trimming, the following circuit is recommended:
where:
RX is in k, CX is in pF t is in ns for CX < 10 pF, see Figure 1.
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for K vs. CX see Figure 6. 4. If electrolytic type capacitors are to be used, the following three configurations are recommended: 1. Use with low leakage capacitors: The normal RC configuration can be used predictably only if the forward capacitor leakage at 5.0V is less than 3 A, and the inverse capacitor leakage at 1.0V is less than 5 A over the operational temperature range.
Input to Pin 5(11), Pin 4(12) = LOW t1, t3 = Min. Positive Input Pulse Width > 40 ns t2, t4 = Min. Negative Input Pulse Width > 40 ns (Pin 3(13) = HIGH)
Input to Pin 4(12) R < 0.6 RX (Max) Pin 5(11) = HIGH
(Pin 3(13) = HIGH)
2. Use with high inverse leakage current electrolytic capacitors: The diode in this configuration prevents high inverse leakage currents through the capacitor by preventing an inverse voltage across the capacitor. The use of this configuration is not recommended with retriggerable operation. t 0.3 RCX
8. The retriggerable pulse width is calculated as shown below:
The retrigger pulse width is equal to the pulse width (t) plus a delay time. For pulse widths greater than 500 ns, tW can be approximated as t. Retriggering will not occur if the retrigger pulse comes within 0.3 CX (ns) after the initial trigger pulse (i.e., during the discharge cycle).
3. Use to obtain extended pulse widths: This configuration can be used to obtain extended pulse widths, because of the larger timing resistor allowed by beta multiplication. Electrolytics with high inverse leakage currents can be used. R < RX (0.7) (hFE Q1) or < 2.5 M, whichever is the lesser RX (min) < RY < RX (max) (5 k RY 10 k is recommended) Q1: NPN silicon transistor with hFE requirements of above equations, such as 2N5961 or 2N5962. t 0.3 RCX
9. Reset Operation--An overriding clear (active LOW level) is provided on each one shot. By applying a LOW to the reset, any timing cycle can be terminated or any new cycle inhibited until the LOW reset input is removed. Trigger inputs will not produce spikes in the output when the reset is held LOW.
10. VCC and Ground wiring should conform to good high frequency standards so that switching transients on VCC and Ground leads do not cause interaction between one shots. Use of a 0.01 to 0.1 F bypass capacitor between VCC and Ground located near the DM9602 is recommended.
Note 1: For further detailed device characteristics and output performance, please refer to the NSC one-shot application note, AN-366.
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DM9602
Typical Performance Characteristics
FIGURE 1. Output Pulse Width vs. Timing Resistance and Capacitance for CX < 103 pF
FIGURE 4. Normalized Output Pulse Width vs. Supply Voltage
FIGURE 2. Normalized Output Pulse Width vs. Ambient Temperature
FIGURE 5. Minimum Output Pulse Width vs. Ambient Temperature
FIGURE 3. Pulse Width vs. Timing Resistor
FIGURE 6. Typical "K" Coefficient Variation vs. Timing Capacitance
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DM9602
Absolute Maximum Ratings(Note 2)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C
Note 2: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH Supply Voltage HIGH Level Input Voltage TA = -55C TA = 0C TA = 25C TA = 75C TA = 125C VIL LOW Level Input Voltage TA = -55C TA = 0C TA = 25C TA = 75C TA = 125C IOH IOL TA HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 -0.8 16 75 mA mA C 0.85 0.85 0.85 V 1.9 1.8 1.65 V Parameter Min 4.75 Nom 5 Max 5.25 Units V
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions (Note 3) VCC = Min, II = -12 mA VCC = Min, IOH = Max VIL = Max, VIH = Min (Note 5) VCC = Min, IOL = Max VIL = Max, VIH = Min (Note 5) VCC = Max, VI = 4.5V VCC = Max VCC = Min VCC = Max VI = 0.45V VI = 0.45V 39 60 -1.6 -1.41 -35 50 2.4 0.45 Min Typ (Note 4) Max -1.5 Units V V V A mA mA mA
VCC = Max, VOUT = 1V (Note 5)(Note 6)
Note 3: Unless otherwise noted, RX = 10k for all tests. Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Ground PIN 1(15) for VOL on PIN 7(9) or VOH and IOS on PIN 6(10) and apply momentary ground to PIN 4(12). Open PIN 1(15) for VOL on PIN 6(10) or VOH and IOS on PIN 7(9). Note 6: Not more than one output should be shorted at a time.
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DM9602
Switching Characteristics
VCC = 5V, TA = 25C Symbol tPLH tPHL tPW(MIN) Propagation Delay Time, LOW-to-HIGH Level Output Propagation Delay Time, HIGH-to-LOW Level Output Minimum True Output Pulse Width Minimum Complement Pulse Width tPW CSTRAY RX Pulse Width Maximum Allowable Wiring Capacitance External Timing Resistor RX = 10 k CX = 1000 pF Pins 2, 14 to GND 5 3.08 Parameter Negative Trigger Input to True Output Negative Trigger Input To Complement Output Conditions CL = 15 pF CX = 0 RX = 5 k Min Max 40 48 100 ns 110 3.76 50 50 s pF k Units ns ns
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DM9602 Dual Retriggerable, Resettable One Shots
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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